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PLL620-05/-06/-07/-08/-09 om c XO with multipliers (for 120-200MHz Fund Xtal) . Low Phase Noise U Universal Low Phase Noise IC's t4 ee FEATURES h PIN CONFIGURATION S (Top View) * 120MHz to 200MHz Fundamental Mode Crystal. ta * Output a range: 120 - 200MHz (no multiplication), 240 D400MHz (2x multiplier) or 480 - 700MHz - .multiplier). (4x w *w High yield design support up to 2pF string w* capacitance at 200MHz.PLL620-07 or Selectable CMOS (Standard drive
VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND XIN
* *
GND/ DRIVSEL*
Drive PLL620-06), PECL (Enable low PLL620-08 or Enable high PLL620-05) or LVDS output (PLL620-09). Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP.
DESCRIPTIONS
GND
GND
GND
BLOCK DIAGRAM
SEL
^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS)
OE Q Q
X+ X-
Oscillator Amplifier
PLL (Phase Locked Loop)
OUTPUT ENABLE LOGICAL LEVELS
Part # PLL620-08 PLL620-05 PLL620-06 PLL620-07 PLL620-09
PLL by-pass
OE input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/-07/-09
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
om .c 4U et he aS at .D w w w
1 (Default) Output enabled Rev 10/29/02 Page 1
OE 0 (Default) 1 0
State Output enabled Tri-state Tri-state
GND
PLL620-05/-06/-07/-08/-09 are XO IC specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability.
m o .c U t4 e e h S ta a .D w w w
XOUT SEL3^ SEL2^ OE GND GND
SEL0^
XIN
12
11
10
9
SEL1^
VDD
PLL 620-0x
CLKC VDD CLKT GND GND
13
8 7 6 5
GND CLKC VDD CLKT
XOUT
14 15
PLL620-0x
1 2 3
SEL2^ OE
16
4
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
PIN DESCRIPTIONS
Name
XIN XOUT OE GND DRIVSEL**
Universal Low Phase Noise IC's
TSSOP* Pin number
2 3 6 7,8,9, 10, 14 -
3x3mm QFN* Pin number
13 14 16 1,2,3,4,8,12 12
Type
I I I P I Crystal in connector. Crystal out connector. Output enable pin.
Description
GND (except pin 12 on PLL620-06: DRIVSEL see below). PLL620-06 only: Drive Select Input. This pin has an internal pullup that will default DRIVSEL to `1' when not connect to GND. CMOS output of PLL620-06 will be high drive CMOS when DRIVSEL is set to `0', and will be standard CMOS otherwise. True output PECL (PLL620-08) or LVDS (PLL620-09) (N/C for PLL620-07) Complementary output PECL (PLL620-08) or LVDS (PLL620-09) (CMOS out for PLL620-07).
CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD
11 13
5 7 10 9 15 Not available 6,11
O O
16 15 5 4
1, 12
I I I I
P +3.3V VDD. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND.
* Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL620-06 only.
FREQUENCY SELECTION TABLE
SEL3 1 1 1 SEL2 0 1 1 SEL1 1 1 1 SEL0 1 0 1 Selected Multiplier Fin x 4 Fin x 2 No multiplication
Note: SEL3 is not available (always "1") in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 2
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
Universal Low Phase Noise IC's
SYMBOL
VDD VI VO TS TA TJ
MIN.
VSS-0.5 VSS-0.5 -65 -40
MAX.
7 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications PARAMETERS
Built-in Capacitance Inter-electrode capacitance Oscillation Frequency
SYMBOL
CX+ CXC0 OF
CONDITIONS
120MHz to 200MHz (VDD=3.3V) Fund.
MIN.
MAX.
2 2 2
UNITS
pF
120
200
MHz
3. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS/CMOS
MIN.
3.13
TYP.
MAX.
100/80/40 3.47
UNITS
mA V % mA
@ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd - 1.3V (PECL)
45 45 45
50 50 50 50
55 55 55
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 3
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
4. Jitter specifications PARAMETERS
Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Integrated jitter RMS at 155MHz
*: To be measured
Universal Low Phase Noise IC's
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
MIN.
TYP.
4 25 7* 45* 0.3
MAX.
UNITS
ps
ps ps
5. Phase noise specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
155.52MHz 622.08MHz
@10Hz
-75 -75
@100Hz
-95 -95
@1kHz
-125 -110
@10kHz
-140 -125
@100kHz
-145 -120
UNITS
dBc/Hz
6. CMOS Output Electrical Specifications PARAMETERS
Output High Voltage Output Low Voltage Output High Voltage at CMOS level Output drive current
SYMBOL
VOH VOL VOHC
CONDITIONS
IOH = -12mA (Standard drive) ILO = 12mA (Standard drive) IOH = -4mA (Standard drive) At TTL level (High drive*) At TTL level (Standard drive)
MIN.
2.4
TYP.
MAX.
0.4
UNITS
V V V mA mA
VDD- 0.4 36 12 51 17
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.
7. CMOS Switching Characteristics PARAMETERS
Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive*)
SYMBOL
CONDITIONS
0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load
MIN.
TYP.
1.15 3.7 0.5 1.5
MAX.
UNITS
ns
* Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 4
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
8. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current 9. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
Universal Low Phase Noise IC's TYP. 355 1.4 MAX. 454 50 1.6 1.375 25 10 -8 1.1 1.2 3 1 -5.7 UNITS mV mV V V V mV uA mA
SYMBOL V OD V OD V OH V OL V OS V OS I OXD I OSD
CONDITIONS
MIN. 247 -50
R L = 100 (see figure)
0.9 1.125 0
V out = V DD or GND V DD = 0V
SYMBOL
tr tf
CONDITIONS R L = 100 C L = 10 pF (see figure)
MIN. 0.2 0.2
TYP. 0.7 0.7
MAX. 1.0 1.0
UNITS ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% V DIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 5
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
Universal Low Phase Noise IC's
10. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL V OH V OL CONDITIONS R L = 50 to (V DD - 2V) (see figure) MIN. V DD - 1.025 V DD - 1.620 MAX. UNITS V V
11. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL
tr tf
CONDITIONS @20/80% - PECL @80/20% - PECL
MIN.
TYP. 0.6 0.5
MAX. 1.5 1.5
UNITS ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 6
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
Universal Low Phase Noise IC's
PACKAGE INFORMATION
16 PIN Narrow SOIC, TSSOP ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.35 0.10 0.33 0.19 9.80 3.80 5.80 0.40 1.27 BSC Max. 1.75 0.25 0.51 0.25 10.00 4.00 6.20 1.27 0.45 Min. 0.05 0.19 0.09 4.90 4.30 TSSOP Max. 1.20 0.15 0.30 0.20 5.10 4.50 6.40 BSC 0.75 0.65 BSC B e A1 C L A D E H
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 7
PLL620-05/-06/-07/-08/-09
Low Phase Noise XO with multipliers (for 120-200MHz Fund Xtal)
ORDERING INFORMATION
Universal Low Phase Noise IC's
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL620-0x O C
PART NUMBER
C=COMMERCIAL M=MILITARY
TEMPERATURE
I=INDUSTRAL
PACKAGE TYPE
O=TSSOP Q=QFN
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/29/02 Page 8

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